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 Post subject: VBL/NMI Timing Test ROMs
PostPosted: Sun Nov 06, 2005 3:35 pm 
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Location: Central Texas, USA
I'm finally releasing some new PPU VBL/NMI timing information and test ROMs. These tests brutally test to single PPU clock accuracy, unlike previous PPU timing tests, so there's no room for error here. Please note that these test only one of the random timing arrangements at power-up (there are others with more special cases, but I haven't spent time determining them).

New PPU VBL/NMI Timing Information

vbl_nmi_timing.zip

As usual, post questions about the test ROMs themselves here, and questions about proper PPU operation in a separate thread.


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PostPosted: Mon Nov 07, 2005 10:45 am 
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what does it means blargg "FAILED #0" and a constantly beep?

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PostPosted: Mon Nov 07, 2005 1:07 pm 
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It means something's really messed up. :)

Which test does that occur on? My guess is that somehow one of the NMI handlers is firing way before I expect it to, which is causing it to use an uninitialized error code. I'll have to add a fix for that to my test framework.


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PostPosted: Mon Nov 07, 2005 5:01 pm 
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it happened on test 1, but only when i decrese scanline cycles, i.e: short vblank time.

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PostPosted: Mon Nov 07, 2005 5:38 pm 
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Thanks for the info. I just checked and the first two tests in ROM 1 don't properly set the result code, so if they fail they'll print an erroneous code as you encountered. I've updated the original archive with this fix.


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PostPosted: Sun Jun 05, 2011 8:29 pm 
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I'm failing basic tests #4. Is all the info for passing the tests in that link there?


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